/*******************************************************************************
 *                                    ZLG
 *                         ----------------------------
 *                         innovating embedded platform
 *
 * Copyright (c) 2001-present Guangzhou ZHIYUAN Electronics Co., Ltd.
 * All rights reserved.
 *
 * Contact information:
 * web site:    https://www.zlg.cn
 *******************************************************************************/
#ifndef __HPM6E00_REGS_TSW_H
#define __HPM6E00_REGS_TSW_H

#ifdef __cplusplus
extern "C" {
#endif  /* __cplusplus*/

#include "core/include/hpm6e00_regs_base.h"
#include <stdint.h>


#define TSW_TSNPORT_MAC_MAC_MDIO_CTRL_OP_MASK           (0x3U << TSW_TSNPORT_MAC_MAC_MDIO_CTRL_OP_POS)
#define TSW_TSNPORT_MAC_MAC_MDIO_CTRL_OP_POS            (30U)
#define TSW_TSNPORT_MAC_MAC_MDIO_CTRL_PHYAD_MASK        (0x1FUL << TSW_TSNPORT_MAC_MAC_MDIO_CTRL_PHYAD_POS)
#define TSW_TSNPORT_MAC_MAC_MDIO_CTRL_PHYAD_POS         (24U)
#define TSW_TSNPORT_MAC_MAC_MDIO_CTRL_REGAD_MASK        (0x1FUL << TSW_TSNPORT_MAC_MAC_MDIO_CTRL_REGAD_POS)
#define TSW_TSNPORT_MAC_MAC_MDIO_CTRL_REGAD_POS         (16U)
#define TSW_TSNPORT_MAC_MAC_MDIO_CTRL_INIT_MASK         (0x1U << TSW_TSNPORT_MAC_MAC_MDIO_CTRL_INIT_POS)
#define TSW_TSNPORT_MAC_MAC_MDIO_CTRL_INIT_POS          (8U)
#define TSW_TSNPORT_MAC_MAC_MDIO_CTRL_READY_MASK        (0x1U)
#define TSW_TSNPORT_MAC_MAC_MDIO_CTRL_READY_POS         (0U)

#define TSW_TSNPORT_MAC_MAC_MDIO_RD_DATA_RD_DATA_MASK   (0xFFFFU)
#define TSW_TSNPORT_MAC_MAC_MDIO_RD_DATA_RD_DATA_POS    (0U)

#define TSW_TSNPORT_MAC_MAC_MDIO_CFG_ENABLE_MASK        (0x1U << TSW_TSNPORT_MAC_MAC_MDIO_CFG_ENABLE_POS)
#define TSW_TSNPORT_MAC_MAC_MDIO_CFG_ENABLE_POS         (8U)
#define TSW_TSNPORT_MAC_MAC_MDIO_CFG_MDC_CLKDIV_MASK    (0xFFU)
#define TSW_TSNPORT_MAC_MAC_MDIO_CFG_MDC_CLKDIV_POS     (0U)

#define TSW_TSNPORT_MAC_MAC_MAC_CTRL_CLKSEL_MASK        (0x7U << TSW_TSNPORT_MAC_MAC_MAC_CTRL_CLKSEL_POS)
#define TSW_TSNPORT_MAC_MAC_MAC_CTRL_CLKSEL_POS         (8U)
#define TSW_TSNPORT_MAC_MAC_MAC_CTRL_PHYSEL_MASK        (0x3U << TSW_TSNPORT_MAC_MAC_MAC_CTRL_PHYSEL_POS)
#define TSW_TSNPORT_MAC_MAC_MAC_CTRL_PHYSEL_POS         (5U)
#define TSW_TSNPORT_MAC_MAC_MAC_CTRL_GMIIMODE_MASK      (0x1U << TSW_TSNPORT_MAC_MAC_MAC_CTRL_GMIIMODE_POS)
#define TSW_TSNPORT_MAC_MAC_MAC_CTRL_GMIIMODE_POS       (4U)
#define TSW_TSNPORT_MAC_MAC_MAC_CTRL_TX_EN_MASK         (0x1U << TSW_TSNPORT_MAC_MAC_MAC_CTRL_TX_EN_POS)
#define TSW_TSNPORT_MAC_MAC_MAC_CTRL_TX_EN_POS          (2U)
#define TSW_TSNPORT_MAC_MAC_MAC_CTRL_RX_EN_MASK         (0x1U << TSW_TSNPORT_MAC_MAC_MAC_CTRL_RX_EN_POS)
#define TSW_TSNPORT_MAC_MAC_MAC_CTRL_RX_EN_POS          (1U)
#define TSW_TSNPORT_MAC_MAC_MAC_CTRL_RESSTAT_MASK       (0x1U)
#define TSW_TSNPORT_MAC_MAC_MAC_CTRL_RESSTAT_POS        (0U)

#define TSW_TSNPORT_MAC_MAC_MACADDR_H_PROMISC_MASK      (0x1U << TSW_TSNPORT_MAC_MAC_MACADDR_H_PROMISC_POS)
#define TSW_TSNPORT_MAC_MAC_MACADDR_H_PROMISC_POS       (16U)

#define TSW_TSNPORT_GPR_CTRL0_RXCLK_DLY_SEL_MASK        (0x3FU << TSW_TSNPORT_GPR_CTRL0_RXCLK_DLY_SEL_POS)
#define TSW_TSNPORT_GPR_CTRL0_RXCLK_DLY_SEL_POS         (8U)
#define TSW_TSNPORT_GPR_CTRL0_TXCLK_DLY_SEL_MASK        (0x3FU)
#define TSW_TSNPORT_GPR_CTRL0_TXCLK_DLY_SEL_POS         (0U)

#define TSW_TSNPORT_GPR_CTRL2_MAC_SPEED_MASK            (0x3U << TSW_TSNPORT_GPR_CTRL2_MAC_SPEED_POS)
#define TSW_TSNPORT_GPR_CTRL2_MAC_SPEED_POS             (20U)
#define TSW_TSNPORT_GPR_CTRL2_PAD_OE_ETH_REFCLK_MASK    (0x1U << TSW_TSNPORT_GPR_CTRL2_PAD_OE_ETH_REFCLK_POS)
#define TSW_TSNPORT_GPR_CTRL2_PAD_OE_ETH_REFCLK_POS     (19U)
#define TSW_TSNPORT_GPR_CTRL2_PHY_INTF_SEL_MASK         (0x7U << TSW_TSNPORT_GPR_CTRL2_PHY_INTF_SEL_POS)
#define TSW_TSNPORT_GPR_CTRL2_PHY_INTF_SEL_POS          (13U)
#define TSW_TSNPORT_GPR_CTRL2_RMII_TXCLK_SEL_MASK       (0x1U << TSW_TSNPORT_GPR_CTRL2_RMII_TXCLK_SEL_POS)
#define TSW_TSNPORT_GPR_CTRL2_RMII_TXCLK_SEL_POS        (10U)

#define TSW_LU_MAIN_HITMEM_CAMMEMCLR_MASK               (0x1U << TSW_LU_MAIN_HITMEM_CAMMEMCLR_POS)
#define TSW_LU_MAIN_HITMEM_CAMMEMCLR_POS                (1U)

#define TSW_MM2S_DMA_SR_RBUFE_MASK                      (0x1U << TSW_MM2S_DMA_SR_RBUFE_POS)
#define TSW_MM2S_DMA_SR_RBUFE_POS                       (6U)
#define TSW_MM2S_DMA_SR_CBUFF_MASK                      (0x1U << TSW_MM2S_DMA_SR_CBUFF_POS)
#define TSW_MM2S_DMA_SR_CBUFF_POS                       (5U)
#define TSW_MM2S_DMA_SR_RSET_MASK                       (0x1U << TSW_MM2S_DMA_SR_RSET_POS)
#define TSW_MM2S_DMA_SR_RSET_POS                        (2U)

#define TSW_MM2S_DMA_CR_MXLEN_MASK                      (0xFFU << TSW_MM2S_DMA_CR_MXLEN_POS)
#define TSW_MM2S_DMA_CR_MXLEN_POS                       (24U)
#define TSW_MM2S_DMA_CR_IRQEN_MASK                      (0x1U << TSW_MM2S_DMA_CR_IRQEN_POS)
#define TSW_MM2S_DMA_CR_IRQEN_POS                       (3U)
#define TSW_MM2S_DMA_CR_RESET_MASK                      (0x1U << TSW_MM2S_DMA_CR_RESET_POS)
#define TSW_MM2S_DMA_CR_RESET_POS                       (2U)
#define TSW_MM2S_DMA_CR_SOE_MASK                        (0x1U << TSW_MM2S_DMA_CR_SOE_POS)
#define TSW_MM2S_DMA_CR_SOE_POS                         (1U)
#define TSW_MM2S_DMA_CR_RUN_MASK                        (0x1U)
#define TSW_MM2S_DMA_CR_RUN_POS                         (0U)

#define TSW_MM2S_CTRL_GO_MASK                           (0x1U << TSW_MM2S_CTRL_GO_POS)
#define TSW_MM2S_CTRL_GO_POS                            (31U)
#define TSW_MM2S_CTRL_ID_MASK                           (0xFU)
#define TSW_MM2S_CTRL_ID_POS                            (0U)

#define TSW_MM2S_RESP_DECERR_MASK                       (0x1U << TSW_MM2S_RESP_DECERR_POS)
#define TSW_MM2S_RESP_DECERR_POS                        (29U)
#define TSW_MM2S_RESP_SLVERR_MASK                       (0x1U << TSW_MM2S_RESP_SLVERR_POS)
#define TSW_MM2S_RESP_SLVERR_POS                        (28U)
#define TSW_MM2S_RESP_ID_MASK                           (0xFU << TSW_MM2S_RESP_ID_POS)
#define TSW_MM2S_RESP_ID_POS                            (24U)

#define TSW_S2MM_DMA_SR_IRQ_MASK                        (0x1U << TSW_S2MM_DMA_SR_IRQ_POS)
#define TSW_S2MM_DMA_SR_IRQ_POS                         (3U)
#define TSW_S2MM_DMA_SR_RSET_MASK                       (0x1U << TSW_S2MM_DMA_SR_RSET_POS)
#define TSW_S2MM_DMA_SR_RSET_POS                        (2U)

#define TSW_S2MM_DMA_CR_MXLEN_MASK                      (0xFFU << TSW_S2MM_DMA_CR_MXLEN_POS)
#define TSW_S2MM_DMA_CR_MXLEN_POS                       (24U)
#define TSW_S2MM_DMA_CR_IRQEN_MASK                      (0x1U << TSW_S2MM_DMA_CR_IRQEN_POS)
#define TSW_S2MM_DMA_CR_IRQEN_POS                       (3U)
#define TSW_S2MM_DMA_CR_RESET_MASK                      (0x1U << TSW_S2MM_DMA_CR_RESET_POS)
#define TSW_S2MM_DMA_CR_RESET_POS                       (2U)
#define TSW_S2MM_DMA_CR_SOE_MASK                        (0x1U << TSW_S2MM_DMA_CR_SOE_POS)
#define TSW_S2MM_DMA_CR_SOE_POS                         (1U)
#define TSW_S2MM_DMA_CR_RUN_MASK                        (0x1U)
#define TSW_S2MM_DMA_CR_RUN_POS                         (0U)

#define TSW_S2MM_CTRL_GO_MASK                           (0x1U << TSW_S2MM_CTRL_GO_POS)
#define TSW_S2MM_CTRL_GO_POS                            (31U)
#define TSW_S2MM_CTRL_ID_MASK                           (0xFU)
#define TSW_S2MM_CTRL_ID_POS                            (0U)

#define TSW_S2MM_RESP_DECERR_MASK                       (0x1U << TSW_S2MM_RESP_DECERR_POS)
#define TSW_S2MM_RESP_DECERR_POS                        (29U)
#define TSW_S2MM_RESP_SLVERR_MASK                       (0x1U << TSW_S2MM_RESP_SLVERR_POS)
#define TSW_S2MM_RESP_SLVERR_POS                        (28U)
#define TSW_S2MM_RESP_ID_MASK                           (0xFU << TSW_S2MM_RESP_ID_POS)
#define TSW_S2MM_RESP_ID_POS                            (24U)
#define TSW_S2MM_RESP_LENGTH_MASK                       (0xFFFFU)
#define TSW_S2MM_RESP_LENGTH_POS                        (0U)

#define TSW_TSNPORT_TSN_SHAPER_TAS_CRSR_OPERGS_MASK     (0xFFUL << TSW_TSNPORT_TSN_SHAPER_TAS_CRSR_OPERGS_POS)
#define TSW_TSNPORT_TSN_SHAPER_TAS_CRSR_OPERGS_POS      (16U)
#define TSW_TSNPORT_TSN_SHAPER_TAS_CRSR_CFGCHG_MASK     (0x1U << TSW_TSNPORT_TSN_SHAPER_TAS_CRSR_CFGCHG_POS)
#define TSW_TSNPORT_TSN_SHAPER_TAS_CRSR_CFGCHG_POS      (1U)
#define TSW_TSNPORT_TSN_SHAPER_TAS_CRSR_EN_MASK         (0x1U)
#define TSW_TSNPORT_TSN_SHAPER_TAS_CRSR_EN_POS          (0U)


#define TSW_TSNPORT_MXTK_TICK_MASK                      (0xFFFFFFUL)
#define TSW_TSNPORT_MXTK_TICK_POS                       (0U)

#define TSW_TSNPORT_SHACL_TSN_SHAPER_ACLIST_ENTRY_L_OP_MASK     (0x3U << TSW_TSNPORT_SHACL_TSN_SHAPER_ACLIST_ENTRY_L_OP_POS)
#define TSW_TSNPORT_SHACL_TSN_SHAPER_ACLIST_ENTRY_L_OP_POS      (8U)
#define TSW_TSNPORT_SHACL_TSN_SHAPER_ACLIST_ENTRY_L_STATE_MASK  (0xFFU)
#define TSW_TSNPORT_SHACL_TSN_SHAPER_ACLIST_ENTRY_L_STATE_POS   (0U)

#define TSW_TSNPORT_SHACL_TSN_SHAPER_ACLIST_ENTRY_H_TIME_MASK   (0xFFFFFFFFUL)
#define TSW_TSNPORT_SHACL_TSN_SHAPER_ACLIST_ENTRY_H_TIME_POS    (0U)

#define TSW_TSNPORT_TSN_SHAPER_TAS_LISTLEN_ALISTLEN_MASK (0xFFU)
#define TSW_TSNPORT_TSN_SHAPER_TAS_LISTLEN_ALISTLEN_POS  (0U)

#define TSW_TSNPORT_TSN_SHAPER_TAS_ACYCLETM_CTIME_MASK (0x3FFFFFFFUL)
#define TSW_TSNPORT_TSN_SHAPER_TAS_ACYCLETM_CTIME_POS  (0U)

#define TSW_TSNPORT_TSN_SHAPER_TAS_ABASETM_L_BASETM_L_MASK  (0x3FFFFFFFUL)
#define TSW_TSNPORT_TSN_SHAPER_TAS_ABASETM_L_BASETM_L_POS   (0U)

#define TSW_TSNPORT_TSN_SHAPER_TAS_ABASETM_H_BASETM_H_MASK  (0xFFFFFFFFUL)
#define TSW_TSNPORT_TSN_SHAPER_TAS_ABASETM_H_BASETM_H_POS   (0U)

#define TSW_APB2AXI_CAM_REQDATA_2_DESTMAC_HI_MASK   (0xFFFFU)
#define TSW_APB2AXI_CAM_REQDATA_2_DESTMAC_HI_POS    (0U)

#define TSW_APB2AXI_CAM_REQDATA_1_DESTMAC_LO_PORT_VEC_MASK (0xFFFFFFFFUL)
#define TSW_APB2AXI_CAM_REQDATA_1_DESTMAC_LO_PORT_VEC_POS  (0U)


#define TSW_APB2AXI_CAM_REQDATA_0_ENTRY_NUM_MASK    (0xFFFF0000UL)
#define TSW_APB2AXI_CAM_REQDATA_0_ENTRY_NUM_POS     (16U)
#define TSW_APB2AXI_CAM_REQDATA_0_TYPE_MASK         (0x300U)
#define TSW_APB2AXI_CAM_REQDATA_0_TYPE_POS          (8U)
#define TSW_APB2AXI_CAM_REQDATA_0_CH_MASK           (0x1U)
#define TSW_APB2AXI_CAM_REQDATA_0_CH_POS            (0U)

#define TSW_APB2AXIS_ALMEM_REQDATA_1_WR_NRD_MASK    (0x1U << TSW_APB2AXIS_ALMEM_REQDATA_1_WR_NRD_POS)
#define TSW_APB2AXIS_ALMEM_REQDATA_1_WR_NRD_POS     (31U)
#define TSW_APB2AXIS_ALMEM_REQDATA_1_ENTRY_NUM_MASK (0xFFFFU)
#define TSW_APB2AXIS_ALMEM_REQDATA_1_ENTRY_NUM_POS  (0U)

#define TSW_APB2AXIS_ALMEM_REQDATA_0_UTAG_MASK      (0x1C00000UL)
#define TSW_APB2AXIS_ALMEM_REQDATA_0_UTAG_POS       (22U)
#define TSW_APB2AXIS_ALMEM_REQDATA_0_QSEL_MASK      (0x3U << TSW_APB2AXIS_ALMEM_REQDATA_0_QSEL_POS)
#define TSW_APB2AXIS_ALMEM_REQDATA_0_QSEL_POS       (20U)
#define TSW_APB2AXIS_ALMEM_REQDATA_0_DROP_MASK      (0x1U << TSW_APB2AXIS_ALMEM_REQDATA_0_DROP_POS)
#define TSW_APB2AXIS_ALMEM_REQDATA_0_DROP_POS       (19U)
#define TSW_APB2AXIS_ALMEM_REQDATA_0_QUEUE_MASK     (0x7U << TSW_APB2AXIS_ALMEM_REQDATA_0_QUEUE_POS)
#define TSW_APB2AXIS_ALMEM_REQDATA_0_QUEUE_POS      (16U)
#define TSW_APB2AXIS_ALMEM_REQDATA_0_DEST_MASK      (0xFFFFU)
#define TSW_APB2AXIS_ALMEM_REQDATA_0_DEST_POS       (0U)

#define TSW_APB2AXIS_ALMEM_STS_RDY_MASK             (0x1U)
#define TSW_APB2AXIS_ALMEM_STS_RDY_POS              (0U)

#define TSW_APB2AXI_CAM_REQDATA_2_VID_MASK (0xFFFU << TSW_APB2AXI_CAM_REQDATA_2_VID_POS)
#define TSW_APB2AXI_CAM_REQDATA_2_VID_POS  (16U)

typedef struct {
    volatile const  uint8_t  RESERVED0[4];                /* 0x0 - 0x3: Reserved */
    volatile uint32_t LU_MAIN_CTRL;                /* 0x4: LU_MAIN control */
    volatile uint32_t LU_MAIN_HITMEM;              /* 0x8: LU_MAIN hit */
    volatile const  uint32_t LU_MAIN_PARAM;               /* 0xC: LU_MAIN parameter */
    volatile uint32_t LU_MAIN_BYPASS;              /* 0x10: LU_MAIN bypass */
    volatile uint32_t LU_MAIN_PCP_REMAP;           /* 0x14: LU_MAIN PCP remap */
    volatile const  uint32_t LU_MAIN_VERSION;             /* 0x18: LU_MAIN version */
    volatile const  uint8_t  RESERVED1[4];                /* 0x1C - 0x1F: Reserved */
    volatile uint32_t LU_MAIN_INTF_ACTION;         /* 0x20: LU_MAIN low word of action data for internal frames */
    volatile const  uint8_t  RESERVED2[4];                /* 0x24 - 0x27: Reserved */
    volatile uint32_t LU_MAIN_BC_ACTION;           /* 0x28: LU_MAIN low word of action data for broadcast frames */
    volatile const  uint8_t  RESERVED3[4];                /* 0x2C - 0x2F: Reserved */
    volatile uint32_t LU_MAIN_NN_ACTION;           /* 0x30: LU_MAIN low word of  action data for unknown frames */
    volatile const  uint8_t  RESERVED4[204];              /* 0x34 - 0xFF: Reserved */
    volatile const  uint32_t APB2AXIS_CAM_STS;            /* 0x100: status register */
    volatile const  uint8_t  RESERVED5[12];               /* 0x104 - 0x10F: Reserved */
    volatile const  uint32_t APB2AXIS_CAM_REQ_CNT;        /* 0x110: request count */
    volatile const  uint32_t APB2AXIS_CAM_FILLSTS;        /* 0x114: fill status */
    volatile  uint32_t APB2AXIS_CAM_RESET;          /* 0x118: reset */
    volatile const  uint32_t APB2AXIS_CAM_PARAM;          /* 0x11C: parameter */
    volatile uint32_t APB2AXI_CAM_REQDATA_0;       /* 0x120: data0 */
    volatile uint32_t APB2AXI_CAM_REQDATA_1;       /* 0x124: data1 */
    volatile uint32_t APB2AXI_CAM_REQDATA_2;       /* 0x128: data2 */
    volatile const  uint8_t  RESERVED6[212];              /* 0x12C - 0x1FF: Reserved */
    volatile const  uint32_t APB2AXIS_ALMEM_STS;          /* 0x200: status register */
    volatile const  uint8_t  RESERVED7[12];               /* 0x204 - 0x20F: Reserved */
    volatile const  uint32_t APB2AXIS_ALMEM_REQ_CNT;      /* 0x210: request count */
    volatile const  uint32_t APB2AXIS_ALMEM_FILLSTS;      /* 0x214: fill status */
    volatile  uint32_t APB2AXIS_ALMEM_RESET;        /* 0x218: reset */
    volatile const  uint32_t APB2AXIS_ALMEM_PARAM;        /* 0x21C: parameter */
    volatile uint32_t APB2AXIS_ALMEM_REQDATA_0;    /* 0x220: data0 */
    volatile uint32_t APB2AXIS_ALMEM_REQDATA_1;    /* 0x224: data1 */
    volatile const  uint8_t  RESERVED8[88];               /* 0x228 - 0x27F: Reserved */
    volatile const  uint32_t AXIS2APB_ALMEM_STS;          /* 0x280: status register */
    volatile const  uint8_t  RESERVED9[12];               /* 0x284 - 0x28F: Reserved */
    volatile const  uint32_t AXIS2APB_ALMEM_RESP_CNT;     /* 0x290: response count */
    volatile const  uint32_t AXIS2APB_ALMEM_FILLSTS;      /* 0x294: fill status */
    volatile uint32_t AXIS2APB_ALMEM_RESET;        /* 0x298: reset */
    volatile const  uint32_t AXIS2APB_ALMEM_PARAM;        /* 0x29C: parameter */
    volatile uint32_t AXIS2APB_ALMEM_RESPDATA_0;   /* 0x2A0: data0 */
    volatile uint32_t AXIS2APB_ALMEM_RESPDATA_1;   /* 0x2A4: data1 */
    volatile const  uint8_t  RESERVED10[344];             /* 0x2A8 - 0x3FF: Reserved */
    volatile uint32_t HITMEM[4];                   /* 0x400 - 0x40C: hitmem */
    volatile const  uint8_t  RESERVED11[3056];            /* 0x410 - 0xFFF: Reserved */
    volatile const  uint32_t APB2AXIS_LOOKUP_STS;         /* 0x1000: status register */
    volatile const  uint8_t  RESERVED12[12];              /* 0x1004 - 0x100F: Reserved */
    volatile const  uint32_t APB2AXIS_LOOKUP_REQ_CNT;     /* 0x1010: response count */
    volatile const  uint32_t APB2AXIS_LOOKUP_FILLSTS;     /* 0x1014: fill status */
    volatile uint32_t APB2AXIS_LOOKUP_RESET;       /* 0x1018: reset */
    volatile const  uint32_t APB2AXIS_LOOKUP_PARAM;       /* 0x101C: parameter */
    volatile uint32_t APB2AXIS_LOOKUP_REQDATA_0;   /* 0x1020: LOOKUP REQUEST Register REQ_DATA_0 */
    volatile uint32_t APB2AXIS_LOOKUP_REQDATA_1;   /* 0x1024: LOOKUP REQUEST Register REQ_DATA_1 */
    volatile const  uint8_t  RESERVED13[4];               /* 0x1028 - 0x102B: Reserved */
    volatile uint32_t APB2AXIS_LOOKUP_REQDATA_3;   /* 0x102C: LOOKUP REQUEST Register REQ_DATA_2 */
    volatile const  uint8_t  RESERVED14[80];              /* 0x1030 - 0x107F: Reserved */
    volatile const  uint32_t AXIS2APB_LOOKUP_STS;         /* 0x1080: status register */
    volatile const  uint8_t  RESERVED15[12];              /* 0x1084 - 0x108F: Reserved */
    volatile const  uint32_t AXIS2APB_LOOKUP_RESP_CNT;    /* 0x1090: response count */
    volatile const  uint32_t AXIS2APB_LOOKUP_FILLSTS;     /* 0x1094: fill status */
    volatile uint32_t AXIS2APB_LOOKUP_RESET;       /* 0x1098: reset */
    volatile const  uint32_t AXIS2APB_LOOKUP_PARAM;       /* 0x109C: parameter */
    volatile uint32_t AXIS2APB_LOOKUP_RESPDATA_0;  /* 0x10A0: LOOKUP RESPONSE Data Register */
    volatile const  uint8_t  RESERVED16[4];               /* 0x10A4 - 0x10A7: Reserved */
    volatile uint32_t AXIS2APB_LOOKUP_RESPDATA_1;  /* 0x10A8: LOOKUP RESPONSE Data Register */
    volatile const  uint8_t  RESERVED17[3924];            /* 0x10AC - 0x1FFF: Reserved */
    volatile const  uint32_t CENTRAL_CSR_VERSION;         /* 0x2000: version register */
    volatile const  uint32_t CENTRAL_CSR_PARAM;           /* 0x2004: Parameter Register */
    volatile uint32_t CENTRAL_CSR_CONFIG;          /* 0x2008: Configuration Register */
    volatile const  uint32_t CENTRAL_CSR_CB_PARAM;        /* 0x200C: CB Parameter Register */
    volatile const  uint32_t CENTRAL_CSR_QCI_CTRL_PARAM;  /* 0x2010: QCI Control Parameter Register */
    volatile const  uint8_t  RESERVED18[240];             /* 0x2014 - 0x2103: Reserved */
    volatile const  uint32_t CENTRAL_QCI_HWCFG;           /* 0x2104: PSPF General CTRAL */
    volatile const  uint8_t  RESERVED19[8];               /* 0x2108 - 0x210F: Reserved */
    volatile uint32_t CENTRAL_QCI_FILTERSEL;       /* 0x2110: Filter select index */
    volatile uint32_t CENTRAL_QCI_METERSEL;        /* 0x2114: Flowmeter select index */
    volatile uint32_t CENTRAL_QCI_GATESEL;         /* 0x2118: Gate select index */
    volatile const  uint8_t  RESERVED20[4];               /* 0x211C - 0x211F: Reserved */
    volatile uint32_t CENTRAL_QCI_FCTRL;           /* 0x2120: FILTER SETTING */
    volatile uint32_t CENTRAL_QCI_FSIZE;           /* 0x2124:  */
    volatile const  uint8_t  RESERVED21[24];              /* 0x2128 - 0x213F: Reserved */
    volatile const  uint32_t QCI_CNT[6];                  /* 0x2140 - 0x2154: FILTER COUNTER */
    volatile const  uint8_t  RESERVED22[8];               /* 0x2158 - 0x215F: Reserved */
    volatile uint32_t CENTRAL_QCI_MCTRL;           /* 0x2160: Flow meter settings */
    volatile const  uint8_t  RESERVED23[12];              /* 0x2164 - 0x216F: Reserved */
    volatile uint32_t CENTRAL_QCI_CIR;             /* 0x2170:  */
    volatile uint32_t CENTRAL_QCI_CBS;             /* 0x2174:  */
    volatile uint32_t CENTRAL_QCI_EIR;             /* 0x2178:  */
    volatile uint32_t CENTRAL_QCI_EBS;             /* 0x217C:  */
    volatile uint32_t CENTRAL_QCI_GCTRL;           /* 0x2180: Gate settings */
    volatile uint32_t CENTRAL_QCI_GSTATUS;         /* 0x2184:  */
    volatile uint32_t CENTRAL_QCI_GLISTINDEX;      /* 0x2188:  */
    volatile uint32_t CENTRAL_QCI_LISTLEN;         /* 0x218C:  */
    volatile uint32_t CENTRAL_QCI_ACYCLETM;        /* 0x2190:  */
    volatile uint32_t CENTRAL_QCI_ABASETM_L;       /* 0x2194:  */
    volatile uint32_t CENTRAL_QCI_ABASETM_H;       /* 0x2198:  */
    volatile const  uint8_t  RESERVED24[4];               /* 0x219C - 0x219F: Reserved */
    volatile uint32_t CENTRAL_QCI_AENTRY_CTRL;     /* 0x21A0:  */
    volatile uint32_t CENTRAL_QCI_AENTRY_AENTRY_IVAL; /* 0x21A4:  */
    volatile const  uint32_t CENTRAL_QCI_AENTRY_OCYCLETM; /* 0x21A8:  */
    volatile const  uint32_t CENTRAL_QCI_AENTRY_OBASETM_L;/* 0x21AC:  */
    volatile const  uint32_t CENTRAL_QCI_AENTRY_OBASETM_H;/* 0x21B0:  */
    volatile const  uint8_t  RESERVED25[7756];            /* 0x21B4 - 0x3FFF: Reserved */
    volatile uint32_t MM2S_DMA_CR;                 /* 0x4000: mm2s control register */
    volatile uint32_t MM2S_DMA_SR;                 /* 0x4004: mm2s status */
    volatile const  uint32_t MM2S_DMA_FILL;               /* 0x4008: mm2s dma fill status */
    volatile const  uint8_t  RESERVED26[16];              /* 0x400C - 0x401B: Reserved */
    volatile const  uint32_t MM2S_DMA_CFG;                /* 0x401C: mm2s dma configure */
    volatile uint32_t MM2S_ADDRLO;                 /* 0x4020: mm2s axi address */
    volatile const  uint8_t  RESERVED27[4];               /* 0x4024 - 0x4027: Reserved */
    volatile uint32_t MM2S_LENGTH;                 /* 0x4028: mm2s axi length */
    volatile uint32_t MM2S_CTRL;                   /* 0x402C: mm2s command control */
    volatile const  uint32_t MM2S_RESP;                   /* 0x4030: mm2s response buffer */
    volatile const  uint8_t  RESERVED28[76];              /* 0x4034 - 0x407F: Reserved */
    volatile uint32_t S2MM_DMA_CR;                 /* 0x4080: s2mm dma control */
    volatile uint32_t S2MM_DMA_SR;                 /* 0x4084: s2mm state */
    volatile const  uint32_t S2MM_DMA_FILL;               /* 0x4088: s2mm buffer fill status */
    volatile const  uint8_t  RESERVED29[16];              /* 0x408C - 0x409B: Reserved */
    volatile const  uint32_t S2MM_DMA_CFG;                /* 0x409C: s2mm dma config status */
    volatile uint32_t S2MM_ADDRLO;                 /* 0x40A0: s2mm axi address */
    volatile const  uint8_t  RESERVED30[4];               /* 0x40A4 - 0x40A7: Reserved */
    volatile uint32_t S2MM_LENGTH;                 /* 0x40A8: s2mm axi length */
    volatile uint32_t S2MM_CTRL;                   /* 0x40AC: s2mm command control */
    volatile const  uint32_t S2MM_RESP;                   /* 0x40B0: s2mm response buffer */
    volatile const  uint8_t  RESERVED31[8012];            /* 0x40B4 - 0x5FFF: Reserved */
    volatile uint32_t PTP_EVT_TS_CTL;              /* 0x6000: timestamp control */
    volatile const  uint8_t  RESERVED32[4];               /* 0x6004 - 0x6007: Reserved */
    volatile const  uint32_t PTP_EVT_PPS_TOD_SEC;         /* 0x6008: pps tod seconds */
    volatile const  uint32_t PTP_EVT_PPS_TOD_NS;          /* 0x600C: pps tod sun seconds */
    volatile const  uint8_t  RESERVED33[12];              /* 0x6010 - 0x601B: Reserved */
    volatile uint32_t PTP_EVT_SCP_SEC0;            /* 0x601C: target time seconds */
    volatile uint32_t PTP_EVT_SCP_NS0;             /* 0x6020: target time sub seconds */
    volatile const  uint8_t  RESERVED34[4];               /* 0x6024 - 0x6027: Reserved */
    volatile const  uint32_t PTP_EVT_TMR_STS;             /* 0x6028: timer status */
    volatile uint32_t PTP_EVT_PPS_CMD;             /* 0x602C: pps command control */
    volatile const  uint32_t PTP_EVT_ATSLO;               /* 0x6030: auxiliray read data sub seconds */
    volatile const  uint32_t PTP_EVT_ATSHI;               /* 0x6034: auxiliray read data seconds */
    volatile const  uint8_t  RESERVED35[40];              /* 0x6038 - 0x605F: Reserved */
    volatile uint32_t PTP_EVT_PPS0_INTERVAL;       /* 0x6060: pps0 interval configure */
    volatile uint32_t PTP_EVT_PPS0_WIDTH;          /* 0x6064: pps0 width configure */
    volatile const  uint8_t  RESERVED36[24];              /* 0x6068 - 0x607F: Reserved */
    volatile uint32_t PTP_EVT_SCP_SEC1;            /* 0x6080: target time seconds */
    volatile uint32_t PTP_EVT_SCP_NS1;             /* 0x6084: target time sub seconds */
    volatile uint32_t PTP_EVT_PPS1_INTERVAL;       /* 0x6088: pps1 interval configure */
    volatile uint32_t PTP_EVT_PPS1_WIDTH;          /* 0x608C: pps1 width configure */
    volatile const  uint8_t  RESERVED37[16];              /* 0x6090 - 0x609F: Reserved */
    volatile uint32_t PTP_EVT_SCP_SEC2;            /* 0x60A0: target time seconds */
    volatile uint32_t PTP_EVT_SCP_NS2;             /* 0x60A4: target time sub seconds */
    volatile uint32_t PTP_EVT_PPS2_INTERVAL;       /* 0x60A8: pps2 interval configure */
    volatile uint32_t PTP_EVT_PPS2_WIDTH;          /* 0x60AC: pps2 width configure */
    volatile const  uint8_t  RESERVED38[16];              /* 0x60B0 - 0x60BF: Reserved */
    volatile uint32_t PTP_EVT_SCP_SEC3;            /* 0x60C0: target time seconds */
    volatile uint32_t PTP_EVT_SCP_NS3;             /* 0x60C4: target time sub seconds */
    volatile uint32_t PTP_EVT_PPS3_INTERVAL;       /* 0x60C8: pps3 interval configure */
    volatile uint32_t PTP_EVT_PPS3_WIDTH;          /* 0x60CC: pps3 width configure */
    volatile const  uint8_t  RESERVED39[16];              /* 0x60D0 - 0x60DF: Reserved */
    volatile uint32_t PTP_EVT_PPS_CTRL0;           /* 0x60E0: pps control 0 register */
    volatile uint32_t PTP_EVT_PPS_SEL;             /* 0x60E4:  */
    volatile const  uint8_t  RESERVED40[8];               /* 0x60E8 - 0x60EF: Reserved */
    volatile uint32_t SOFT_RST_CTRL;               /* 0x60F0: softer reset control */
    volatile const  uint8_t  RESERVED41[40716];           /* 0x60F4 - 0xFFFF: Reserved */
    volatile uint32_t CPU_PORT_PORT_MAIN_TAGGING;  /* 0x10000: PVID Tagging Register */
    volatile uint32_t CPU_PORT_PORT_MAIN_ENNABLE;  /* 0x10004: Port Module Enable Register */
    volatile const  uint8_t  RESERVED42[10232];           /* 0x10008 - 0x127FF: Reserved */
    volatile uint32_t CPU_PORT_EGRESS_STMID_ESELECT; /* 0x12800: Stream Identification */
    volatile const  uint8_t  RESERVED43[60];              /* 0x12804 - 0x1283F: Reserved */
    volatile uint32_t CPU_PORT_EGRESS_STMID_CONTROL; /* 0x12840:  */
    volatile uint32_t CPU_PORT_EGRESS_STMID_SEQNO; /* 0x12844:  */
    volatile uint32_t CPU_PORT_EGRESS_STMID_MATCHCNT; /* 0x12848:  */
    volatile const  uint8_t  RESERVED44[4];               /* 0x1284C - 0x1284F: Reserved */
    volatile uint32_t CPU_PORT_EGRESS_STMID_MACLO; /* 0x12850:  */
    volatile uint32_t CPU_PORT_EGRESS_STMID_MACHI; /* 0x12854:  */
    volatile uint32_t CPU_PORT_EGRESS_STMID_AMACLO;/* 0x12858:  */
    volatile uint32_t CPU_PORT_EGRESS_STMID_AMACHI;/* 0x1285C:  */
    volatile const  uint8_t  RESERVED45[160];             /* 0x12860 - 0x128FF: Reserved */
    volatile uint32_t CPU_PORT_EGRESS_FRER_CONTROL;/* 0x12900: Frame Replication and Elimination */
    volatile uint32_t CPU_PORT_EGRESS_FRER_SIDSEL; /* 0x12904:  */
    volatile uint32_t CPU_PORT_EGRESS_FRER_IRFUNC; /* 0x12908:  */
    volatile uint32_t CPU_PORT_EGRESS_FRER_SRFUNC; /* 0x1290C:  */
    volatile uint32_t CPU_PORT_EGRESS_FRER_FSELECT;/* 0x12910:  */
    volatile const  uint8_t  RESERVED46[44];              /* 0x12914 - 0x1293F: Reserved */
    volatile uint32_t CPU_PORT_EGRESS_FRER_FCTRL;  /* 0x12940:  */
    volatile uint32_t CPU_PORT_EGRESS_FRER_RESETMSEC; /* 0x12944:  */
    volatile uint32_t CPU_PORT_EGRESS_FRER_LATRSPERIOD; /* 0x12948:  */
    volatile uint32_t CPU_PORT_EGRESS_FRER_LATTESTPERIOD; /* 0x1294C:  */
    volatile uint32_t CPU_PORT_EGRESS_FRER_LATERRDIFFALW; /* 0x12950:  */
    volatile uint32_t CPU_PORT_EGRESS_FRER_LATERRCNT; /* 0x12954:  */
    volatile const  uint8_t  RESERVED47[8];               /* 0x12958 - 0x1295F: Reserved */
    volatile const  uint32_t EGFRCNT[8];                  /* 0x12960 - 0x1297C:  */
    volatile const  uint8_t  RESERVED48[5760];            /* 0x12980 - 0x13FFF: Reserved */
    volatile const  uint32_t CPU_PORT_IGRESS_RX_FDFIFO_FDMEM_CNT_BYTE; /* 0x14000:  */
    volatile const  uint32_t CPU_PORT_IGRESS_RX_FDFIFO_FDMEM_STS; /* 0x14004:  */
    volatile uint32_t CPU_PORT_IGRESS_RX_FDFIFO_ERROR_FLAG; /* 0x14008:  */
    volatile uint32_t CPU_PORT_IGRESS_RX_FDFIFO_IE_ERROR_FLAG; /* 0x1400C:  */
    volatile uint32_t CPU_PORT_IGRESS_RX_FDFIFO_IN_CONFIG; /* 0x14010:  */
    volatile uint32_t CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG; /* 0x14014:  */
    volatile  uint32_t CPU_PORT_IGRESS_RX_FDFIFO_RESET; /* 0x14018:  */
    volatile const  uint32_t CPU_PORT_IGRESS_RX_FDFIFO_PARAM; /* 0x1401C:  */
    volatile uint32_t CPU_PORT_IGRESS_RX_FDFIFO_STRFWD; /* 0x14020:  */
    volatile uint32_t CPU_PORT_IGRESS_RX_FDFIFO_PORTMASK; /* 0x14024:  */
    volatile uint32_t CPU_PORT_IGRESS_RX_FDFIFO_MIRROR; /* 0x14028:  */
    volatile uint32_t CPU_PORT_IGRESS_RX_FDFIFO_MIRROR_TX; /* 0x1402C:  */
    volatile const  uint8_t  RESERVED49[2000];            /* 0x14030 - 0x147FF: Reserved */
    volatile uint32_t CPU_PORT_IGRESS_STMID_ESELECT; /* 0x14800: Stream Identification */
    volatile const  uint8_t  RESERVED50[60];              /* 0x14804 - 0x1483F: Reserved */
    volatile uint32_t CPU_PORT_IGRESS_STMID_CONTROL; /* 0x14840:  */
    volatile uint32_t CPU_PORT_IGRESS_STMID_SEQNO; /* 0x14844:  */
    volatile uint32_t CPU_PORT_IGRESS_STMID_MATCHCNT; /* 0x14848:  */
    volatile const  uint8_t  RESERVED51[4];               /* 0x1484C - 0x1484F: Reserved */
    volatile uint32_t CPU_PORT_IGRESS_STMID_MACLO; /* 0x14850:  */
    volatile uint32_t CPU_PORT_IGRESS_STMID_MACHI; /* 0x14854:  */
    volatile uint32_t CPU_PORT_IGRESS_STMID_AMACLO;/* 0x14858:  */
    volatile uint32_t CPU_PORT_IGRESS_STMID_AMACHI;/* 0x1485C:  */
    volatile const  uint8_t  RESERVED52[160];             /* 0x14860 - 0x148FF: Reserved */
    volatile uint32_t CPU_PORT_IGRESS_FRER_CONTROL;/* 0x14900: Frame Replication and Elimination */
    volatile uint32_t CPU_PORT_IGRESS_FRER_SIDSEL; /* 0x14904:  */
    volatile uint32_t CPU_PORT_IGRESS_FRER_IRFUNC; /* 0x14908:  */
    volatile uint32_t CPU_PORT_IGRESS_FRER_SRFUNC; /* 0x1490C:  */
    volatile uint32_t CPU_PORT_IGRESS_FRER_FSELECT;/* 0x14910:  */
    volatile const  uint8_t  RESERVED53[44];              /* 0x14914 - 0x1493F: Reserved */
    volatile uint32_t CPU_PORT_IGRESS_FRER_FCTRL;  /* 0x14940:  */
    volatile uint32_t CPU_PORT_IGRESS_FRER_RESETMSEC; /* 0x14944:  */
    volatile uint32_t CPU_PORT_IGRESS_FRER_LATRSPERIOD; /* 0x14948:  */
    volatile uint32_t CPU_PORT_IGRESS_FRER_LATTESTPERIOD; /* 0x1494C:  */
    volatile uint32_t CPU_PORT_IGRESS_FRER_LATERRDIFFALW; /* 0x14950:  */
    volatile uint32_t CPU_PORT_IGRESS_FRER_LATERRCNT; /* 0x14954:  */
    volatile const  uint8_t  RESERVED54[8];               /* 0x14958 - 0x1495F: Reserved */
    volatile const  uint32_t IGFRCNT[8];                  /* 0x14960 - 0x1497C:  */
    volatile const  uint8_t  RESERVED55[13956];           /* 0x14980 - 0x18003: Reserved */
    volatile uint32_t CPU_PORT_MONITOR_CTRL;       /* 0x18004:  */
    volatile  uint32_t CPU_PORT_MONITOR_RESET;      /* 0x18008:  */
    volatile const  uint32_t CPU_PORT_MONITOR_PARAM;      /* 0x1800C:  */
    volatile const  uint32_t CPU_PORT_MONITOR_TX_COUNTER_TX_FGOOD; /* 0x18010:  */
    volatile const  uint8_t  RESERVED56[4];               /* 0x18014 - 0x18017: Reserved */
    volatile const  uint32_t CPU_PORT_MONITOR_TX_COUNTER_TX_FERROR; /* 0x18018:  */
    volatile const  uint8_t  RESERVED57[4];               /* 0x1801C - 0x1801F: Reserved */
    volatile const  uint32_t CPU_PORT_MONITOR_TX_COUNTER_TX_DROP_OVFL; /* 0x18020:  */
    volatile const  uint8_t  RESERVED58[28];              /* 0x18024 - 0x1803F: Reserved */
    volatile const  uint32_t CPU_PORT_MONITOR_RX_COUNTER_RX_FGOOD; /* 0x18040:  */
    volatile const  uint8_t  RESERVED59[4];               /* 0x18044 - 0x18047: Reserved */
    volatile const  uint32_t CPU_PORT_MONITOR_RX_COUNTER_RX_FERROR; /* 0x18048:  */
    volatile const  uint8_t  RESERVED60[4];               /* 0x1804C - 0x1804F: Reserved */
    volatile const  uint32_t CPU_PORT_MONITOR_RX_COUNTER_RX_KNOWN; /* 0x18050:  */
    volatile const  uint8_t  RESERVED61[4];               /* 0x18054 - 0x18057: Reserved */
    volatile const  uint32_t CPU_PORT_MONITOR_RX_COUNTER_RX_UNKNOWN; /* 0x18058:  */
    volatile const  uint8_t  RESERVED62[4];               /* 0x1805C - 0x1805F: Reserved */
    volatile const  uint32_t CPU_PORT_MONITOR_RX_COUNTER_RX_UC; /* 0x18060:  */
    volatile const  uint8_t  RESERVED63[4];               /* 0x18064 - 0x18067: Reserved */
    volatile const  uint32_t CPU_PORT_MONITOR_RX_COUNTER_RX_INTERN; /* 0x18068:  */
    volatile const  uint8_t  RESERVED64[4];               /* 0x1806C - 0x1806F: Reserved */
    volatile const  uint32_t CPU_PORT_MONITOR_RX_COUNTER_RX_BC; /* 0x18070:  */
    volatile const  uint8_t  RESERVED65[4];               /* 0x18074 - 0x18077: Reserved */
    volatile const  uint32_t CPU_PORT_MONITOR_RX_COUNTER_RX_MULTI; /* 0x18078:  */
    volatile const  uint8_t  RESERVED66[4];               /* 0x1807C - 0x1807F: Reserved */
    volatile const  uint32_t CPU_PORT_MONITOR_RX_COUNTER_RX_VLAN; /* 0x18080:  */
    volatile const  uint8_t  RESERVED67[4];               /* 0x18084 - 0x18087: Reserved */
    volatile const  uint32_t CPU_PORT_MONITOR_RX_COUNTER_RX_DROP_OVFL; /* 0x18088:  */
    volatile const  uint8_t  RESERVED68[4];               /* 0x1808C - 0x1808F: Reserved */
    volatile const  uint32_t CPU_PORT_MONITOR_RX_COUNTER_RX_DROP_LU; /* 0x18090:  */
    volatile const  uint8_t  RESERVED69[4];               /* 0x18094 - 0x18097: Reserved */
    volatile const  uint32_t CPU_PORT_MONITOR_RX_COUNTER_RX_DROP_ERR; /* 0x18098:  */
    volatile const  uint8_t  RESERVED70[4];               /* 0x1809C - 0x1809F: Reserved */
    volatile const  uint32_t CPU_PORT_MONITOR_RX_COUNTER_RX_DROP_VLAN; /* 0x180A0:  */
    volatile const  uint8_t  RESERVED71[4];               /* 0x180A4 - 0x180A7: Reserved */
    volatile const  uint32_t CPU_PORT_MONITOR_RX_COUNTER_RX_FPE_FGOOD; /* 0x180A8:  */
    volatile const  uint8_t  RESERVED72[32596];           /* 0x180AC - 0x1FFFF: Reserved */
    struct {
        struct {
            volatile const  uint32_t MAC_VER;             /* 0x20000:  */
            volatile uint32_t MAC_MACADDR_L;       /* 0x20004:  */
            volatile uint32_t MAC_MACADDR_H;       /* 0x20008:  */
            volatile uint32_t MAC_MAC_CTRL;        /* 0x2000C:  */
            volatile const  uint32_t MAC_TX_FRAMES;       /* 0x20010:  */
            volatile const  uint32_t MAC_RX_FRAMES;       /* 0x20014:  */
            volatile const  uint32_t MAC_TX_OCTETS;       /* 0x20018:  */
            volatile const  uint32_t MAC_RX_OCTETS;       /* 0x2001C:  */
            volatile uint32_t MAC_MDIO_CFG;        /* 0x20020:  */
            volatile uint32_t MAC_MDIO_CTRL;       /* 0x20024:  */
            volatile const  uint32_t MAC_MDIO_RD_DATA;    /* 0x20028:  */
            volatile uint32_t MAC_MDIO_WR_DATA;    /* 0x2002C:  */
            volatile uint32_t MAC_IRQ_CTRL;        /* 0x20030:  */
            volatile const  uint8_t  RESERVED0[460];      /* 0x20034 - 0x201FF: Reserved */
        } MAC[2];
        volatile const  uint8_t  RESERVED0[1024];         /* 0x20400 - 0x207FF: Reserved */
        volatile uint32_t RTC_CR;                  /* 0x20800: ONLY IN PORT1 */
        volatile uint32_t RTC_SR;                  /* 0x20804: ONLY IN PORT1 */
        volatile const  uint8_t  RESERVED1[8];            /* 0x20808 - 0x2080F: Reserved */
        volatile uint32_t RTC_CT_CURTIME_NS;       /* 0x20810: ONLY IN PORT1 */
        volatile const  uint32_t RTC_CT_CURTIME_SEC;      /* 0x20814: ONLY IN PORT1 */
        volatile const  uint8_t  RESERVED2[4];            /* 0x20818 - 0x2081B: Reserved */
        volatile uint32_t RTC_CT_TIMER_INCR;       /* 0x2081C: ONLY IN PORT1 */
        volatile uint32_t RTC_OFS_NS;              /* 0x20820: ONLY IN PORT1 */
        volatile uint32_t RTC_OFS_SL;              /* 0x20824: ONLY IN PORT1 */
        volatile uint32_t RTC_OFS_SH;              /* 0x20828: ONLY IN PORT1 */
        volatile uint32_t RTC_OFS_CH;              /* 0x2082C: ONLY IN PORT1 */
        volatile uint32_t RTC_ALARM_NS;            /* 0x20830: ONLY IN PORT1 */
        volatile uint32_t RTC_ALARM_SL;            /* 0x20834: ONLY IN PORT1 */
        volatile uint32_t RTC_ALARM_SH;            /* 0x20838: ONLY IN PORT1 */
        volatile const  uint8_t  RESERVED3[4];            /* 0x2083C - 0x2083F: Reserved */
        volatile uint32_t RTC_TIMER_A_PERIOD;      /* 0x20840: ONLY IN PORT1 */
        volatile const  uint8_t  RESERVED4[1984];         /* 0x20844 - 0x21003: Reserved */
        volatile uint32_t TSYN_CR;                 /* 0x21004:  */
        volatile uint32_t TSYN_SR;                 /* 0x21008:  */
        volatile const  uint8_t  RESERVED5[4];            /* 0x2100C - 0x2100F: Reserved */
        volatile const  uint32_t TSYN_PTP_TX_STS;         /* 0x21010:  */
        volatile uint32_t TSYN_PTP_TX_DONE;        /* 0x21014:  */
        volatile  uint32_t TSYN_PTP_TX_TRIG;        /* 0x21018:  */
        volatile uint32_t TSYN_PTP_RX_STS;         /* 0x2101C:  */
        volatile uint32_t TSYNTMR[5];              /* 0x21020 - 0x21030:  */
        volatile const  uint8_t  RESERVED6[8];            /* 0x21034 - 0x2103B: Reserved */
        volatile uint32_t TSYN_HCLKDIV;            /* 0x2103C:  */
        volatile const  uint8_t  RESERVED7[1472];         /* 0x21040 - 0x215FF: Reserved */
        volatile const  uint32_t TSYN_RXBUF_RX_FRAME_LENGTH_BYTES; /* 0x21600:  */
        volatile const  uint8_t  RESERVED8[4];            /* 0x21604 - 0x21607: Reserved */
        volatile const  uint32_t TSYN_RXBUF_RX_TIME_STAMP_L; /* 0x21608:  */
        volatile const  uint32_t TSYN_RXBUF_RX_TIME_STAMP_H; /* 0x2160C:  */
        volatile const  uint32_t RXDATA[60];              /* 0x21610 - 0x216FC:  */
        volatile const  uint8_t  RESERVED9[256];          /* 0x21700 - 0x217FF: Reserved */
        struct {
            volatile  uint32_t TXDATA[60];          /* 0x21800 - 0x218EC:  */
            volatile  uint32_t TSYN_TXBUF_TQUE_AND_TX_LEN; /* 0x218F0:  */
            volatile const  uint8_t  RESERVED0[4];        /* 0x218F4 - 0x218F7: Reserved */
            volatile const  uint32_t TSYN_TXBUF_TX_TIMESTAMP_L; /* 0x218F8:  */
            volatile const  uint32_t TSYN_TXBUF_TX_TIMESTAMP_H; /* 0x218FC:  */
        } BIN[8];
        volatile const  uint8_t  RESERVED10[4];           /* 0x22000 - 0x22003: Reserved */
        volatile const  uint32_t TSN_SHAPER_HWCFG1;       /* 0x22004:  */
        volatile const  uint8_t  RESERVED11[4];           /* 0x22008 - 0x2200B: Reserved */
        volatile uint32_t TSN_SHAPER_TQAV;         /* 0x2200C:  */
        volatile const  uint32_t TSN_SHAPER_TQEM;         /* 0x22010:  */
        volatile uint32_t TSN_SHAPER_FPST;         /* 0x22014:  */
        volatile uint32_t TSN_SHAPER_MMCT;         /* 0x22018:  */
        volatile uint32_t TSN_SHAPER_HOLDADV;      /* 0x2201C:  */
        volatile const  uint8_t  RESERVED12[224];         /* 0x22020 - 0x220FF: Reserved */
        volatile uint32_t MXSDU[8];                /* 0x22100 - 0x2211C:  */
        volatile uint32_t TXSEL[8];                /* 0x22120 - 0x2213C:  */
        volatile uint32_t IDSEL[8];                /* 0x22140 - 0x2215C:  */
        volatile const  uint8_t  RESERVED13[1696];        /* 0x22160 - 0x227FF: Reserved */
        volatile uint32_t PORT1_QCH0_CFG;          /* 0x22800: qch channel0 control */
        volatile uint32_t PORT1_QCH1_CFG;          /* 0x22804: qch channel1 control */
        volatile uint32_t PORT1_QCH2_CFG;          /* 0x22808: qch channel2 control */
        volatile uint32_t PORT1_QCH3_CFG;          /* 0x2280C: qch channel3 control */
        volatile uint32_t PORT1_QCH_ERR_CFG;       /* 0x22810: qch clear */
        volatile const  uint8_t  RESERVED14[2028];        /* 0x22814 - 0x22FFF: Reserved */
        volatile uint32_t TSN_SHAPER_TAS_CRSR;     /* 0x23000:  */
        volatile uint32_t TSN_SHAPER_TAS_ACYCLETM; /* 0x23004:  */
        volatile uint32_t TSN_SHAPER_TAS_ABASETM_L;/* 0x23008:  */
        volatile uint32_t TSN_SHAPER_TAS_ABASETM_H;/* 0x2300C:  */
        volatile uint32_t TSN_SHAPER_TAS_LISTLEN;  /* 0x23010:  */
        volatile const  uint32_t TSN_SHAPER_TAS_OCYCLETM; /* 0x23014:  */
        volatile const  uint32_t TSN_SHAPER_TAS_OBASETM_L;/* 0x23018:  */
        volatile const  uint32_t TSN_SHAPER_TAS_OBASETM_H;/* 0x2301C:  */
        volatile uint32_t MXTK[8];                 /* 0x23020 - 0x2303C:  */
        volatile uint32_t TXOV[8];                 /* 0x23040 - 0x2305C:  */
        volatile const  uint8_t  RESERVED15[1952];        /* 0x23060 - 0x237FF: Reserved */
        struct {
            volatile uint32_t TSN_SHAPER_ACLIST_ENTRY_L; /* 0x23800:  */
            volatile uint32_t TSN_SHAPER_ACLIST_ENTRY_H; /* 0x23804:  */
        } SHACL[256];
        volatile const  uint8_t  RESERVED16[45056];       /* 0x24000 - 0x2EFFF: Reserved */
        volatile const  uint32_t TSN_EP_VER;              /* 0x2F000:  */
        volatile uint32_t TSN_EP_CTRL;             /* 0x2F004:  */
        volatile const  uint8_t  RESERVED17[8];           /* 0x2F008 - 0x2F00F: Reserved */
        volatile uint32_t TSN_EP_TXUF;             /* 0x2F010:  */
        volatile const  uint32_t TSN_EP_IPCFG;            /* 0x2F014:  */
        volatile const  uint8_t  RESERVED18[8];           /* 0x2F018 - 0x2F01F: Reserved */
        volatile const  uint32_t TSN_EP_TSF_D0;           /* 0x2F020:  */
        volatile const  uint32_t TSN_EP_TSF_D1;           /* 0x2F024:  */
        volatile const  uint32_t TSN_EP_TSF_D2;           /* 0x2F028:  */
        volatile uint32_t TSN_EP_TSF_SR;           /* 0x2F02C:  */
        volatile uint32_t TSN_EP_MMS_CTRL;         /* 0x2F030:  */
        volatile const  uint32_t TSN_EP_MMS_STS;          /* 0x2F034:  */
        volatile uint32_t TSN_EP_MMS_VTIME;        /* 0x2F038:  */
        volatile uint32_t TSN_EP_MMS_STAT;         /* 0x2F03C:  */
        volatile  uint32_t TSN_EP_PTP_UPTM_NS;      /* 0x2F040:  */
        volatile  uint32_t TSN_EP_PTP_UPTM_S;       /* 0x2F044:  */
        volatile const  uint32_t TSN_EP_PTP_SR;           /* 0x2F048:  */
        volatile const  uint8_t  RESERVED19[4020];        /* 0x2F04C - 0x2FFFF: Reserved */
        volatile uint32_t SW_CTRL_PORT_MAIN_TAGGING; /* 0x30000: PVID Tagging Register */
        volatile uint32_t SW_CTRL_PORT_MAIN_ENNABLE; /* 0x30004: Port Module Enable Register */
        volatile const  uint8_t  RESERVED20[8184];        /* 0x30008 - 0x31FFF: Reserved */
        volatile uint32_t SW_CTRL_EGRESS_ECSR_QDROP; /* 0x32000:  */
        volatile const  uint8_t  RESERVED21[8188];        /* 0x32004 - 0x33FFF: Reserved */
        struct {
            volatile const  uint32_t SW_CTRL_IGRESS_RX_FDFIFO_E_FDMEM_CNT_BYTE; /* 0x34000:  */
            volatile const  uint32_t SW_CTRL_IGRESS_RX_FDFIFO_E_FDMEM_STS; /* 0x34004:  */
            volatile uint32_t SW_CTRL_IGRESS_RX_FDFIFO_E_ERROR_FLAG; /* 0x34008:  */
            volatile uint32_t SW_CTRL_IGRESS_RX_FDFIFO_E_IE_ERROR_FLAG; /* 0x3400C:  */
            volatile uint32_t SW_CTRL_IGRESS_RX_FDFIFO_E_IN_CONFIG; /* 0x34010:  */
            volatile uint32_t SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG; /* 0x34014:  */
            volatile  uint32_t SW_CTRL_IGRESS_RX_FDFIFO_E_RESET; /* 0x34018:  */
            volatile const  uint32_t SW_CTRL_IGRESS_RX_FDFIFO_E_PARAM; /* 0x3401C:  */
            volatile uint32_t SW_CTRL_IGRESS_RX_FDFIFO_E_STRFWD; /* 0x34020:  */
            volatile uint32_t SW_CTRL_IGRESS_RX_FDFIFO_E_PORTMASK; /* 0x34024:  */
            volatile uint32_t SW_CTRL_IGRESS_RX_FDFIFO_E_MIRROR; /* 0x34028:  */
            volatile uint32_t SW_CTRL_IGRESS_RX_FDFIFO_E_MIRROR_TX; /* 0x3402C:  */
            volatile const  uint8_t  RESERVED0[208];      /* 0x34030 - 0x340FF: Reserved */
        } RXFIFO[2];
        volatile const  uint8_t  RESERVED22[15876];       /* 0x34200 - 0x38003: Reserved */
        volatile uint32_t SW_CTRL_MONITOR_CTRL;    /* 0x38004:  */
        volatile  uint32_t SW_CTRL_MONITOR_RESET;   /* 0x38008:  */
        volatile const  uint32_t SW_CTRL_MONITOR_PARAM;   /* 0x3800C:  */
        volatile const  uint32_t MONITOR_TX_COUNTER_TX_FGOOD; /* 0x38010:  */
        volatile const  uint8_t  RESERVED23[4];           /* 0x38014 - 0x38017: Reserved */
        volatile const  uint32_t MONITOR_TX_COUNTER_TX_FERROR; /* 0x38018:  */
        volatile const  uint8_t  RESERVED24[4];           /* 0x3801C - 0x3801F: Reserved */
        volatile const  uint32_t MONITOR_TX_COUNTER_TX_DROP_OVFL; /* 0x38020:  */
        volatile const  uint8_t  RESERVED25[28];          /* 0x38024 - 0x3803F: Reserved */
        volatile const  uint32_t MONITOR_RX_COUNTER_RX_FGOOD; /* 0x38040:  */
        volatile const  uint8_t  RESERVED26[4];           /* 0x38044 - 0x38047: Reserved */
        volatile const  uint32_t MONITOR_RX_COUNTER_RX_FERROR; /* 0x38048:  */
        volatile const  uint8_t  RESERVED27[4];           /* 0x3804C - 0x3804F: Reserved */
        volatile const  uint32_t MONITOR_RX_COUNTER_RX_KNOWN; /* 0x38050:  */
        volatile const  uint8_t  RESERVED28[4];           /* 0x38054 - 0x38057: Reserved */
        volatile const  uint32_t MONITOR_RX_COUNTER_RX_UNKNOWN; /* 0x38058:  */
        volatile const  uint8_t  RESERVED29[4];           /* 0x3805C - 0x3805F: Reserved */
        volatile const  uint32_t MONITOR_RX_COUNTER_RX_UC;/* 0x38060:  */
        volatile const  uint8_t  RESERVED30[4];           /* 0x38064 - 0x38067: Reserved */
        volatile const  uint32_t MONITOR_RX_COUNTER_RX_INTERN; /* 0x38068:  */
        volatile const  uint8_t  RESERVED31[4];           /* 0x3806C - 0x3806F: Reserved */
        volatile const  uint32_t MONITOR_RX_COUNTER_RX_BC;/* 0x38070:  */
        volatile const  uint8_t  RESERVED32[4];           /* 0x38074 - 0x38077: Reserved */
        volatile const  uint32_t MONITOR_RX_COUNTER_RX_MULTI; /* 0x38078:  */
        volatile const  uint8_t  RESERVED33[4];           /* 0x3807C - 0x3807F: Reserved */
        volatile const  uint32_t MONITOR_RX_COUNTER_RX_VLAN; /* 0x38080:  */
        volatile const  uint8_t  RESERVED34[4];           /* 0x38084 - 0x38087: Reserved */
        volatile const  uint32_t MONITOR_RX_COUNTER_RX_DROP_OVFL; /* 0x38088:  */
        volatile const  uint8_t  RESERVED35[4];           /* 0x3808C - 0x3808F: Reserved */
        volatile const  uint32_t MONITOR_RX_COUNTER_RX_DROP_LU; /* 0x38090:  */
        volatile const  uint8_t  RESERVED36[4];           /* 0x38094 - 0x38097: Reserved */
        volatile const  uint32_t MONITOR_RX_COUNTER_RX_DROP_ERR; /* 0x38098:  */
        volatile const  uint8_t  RESERVED37[4];           /* 0x3809C - 0x3809F: Reserved */
        volatile const  uint32_t MONITOR_RX_COUNTER_RX_DROP_VLAN; /* 0x380A0:  */
        volatile const  uint8_t  RESERVED38[4];           /* 0x380A4 - 0x380A7: Reserved */
        volatile const  uint32_t MONITOR_RX_COUNTER_RX_FPE_FGOOD; /* 0x380A8:  */
        volatile const  uint8_t  RESERVED39[16212];       /* 0x380AC - 0x3BFFF: Reserved */
        volatile uint32_t GPR_CTRL0;               /* 0x3C000: control register0 */
        volatile const  uint8_t  RESERVED40[4];           /* 0x3C004 - 0x3C007: Reserved */
        volatile uint32_t GPR_CTRL2;               /* 0x3C008: control register2 */
        volatile const  uint8_t  RESERVED41[16372];       /* 0x3C00C - 0x3FFFF: Reserved */
    } TSNPORT[3];
} hpm_tsw_reg_t;

#define HPM_TSW  ((hpm_tsw_reg_t *)HPM_TSW_BASE)

#ifdef __cplusplus
}
#endif  /* __cplusplus  */
#endif

